Experience pays! The company's engineering has been working in SoC and Systems with a combined experience of more than 80 man years. Based on the experience, they have put together tools for the industry for productivity at different levels of SOC design.
Currently, the company provides the following tools:
- Aims PDQA Tool
- Aims UTB Testbench Generator
- Aims RTL Source Protection
The details are given below.
1. Aims PDQA Tool:
If you need a tool to check the integrity of all cell views across PD releases, then this is the tool for you. It checks quality across Verilog, LEF, LIB, GDS, CDL etc. It checks updates between multiple releases of the same views. It does a trend check across LIBs and so on.
The tool comes in handy for any physical design team working either with own internal IPs as well as 3rd party IPs.
2. Aims UTB Testbench Generator:
UTB Testbench Generator tool comes in handy for RTL designers who wants to write block and module level tests for their design using UVM-based TestBench (UTB). The tool generates a UVM testbench that helps the design to write UVM-based tests with a little knowledge of UVM
UTB offers enhanced productivity to verification engineers by reducing the design time spent in creating testbench. The resulting testbench templates are compact and easy to understand. The testbench template compiles and simulates, and thus enables the user to start developing and adding tests.
Currently, UTB supports UVCs for the following industry standard protocols
3. Aims RTL Source Protection Tool:
You want to deliver your IP to the 3rd party synthesis and FPGA team, but do not prefer to release the original source code... Then this Aims RTL IP Protection tool is ideal for you to release the black box RTL for verification, synthesis and PnR.
For tool details and purchase, please contact email@example.com or call 408-981-2453